The present invention relates, in general, to logic circuitry used in electronic devices, and in particular, to latch and register circuitry designed for a Complementary Metal Oxide Semiconductor (CMOS) process including quantum mechanical tunneling structures.
The continual demand for enhanced transistor and integrated circuit performance has resulted in improvements in existing devices, such as silicon, bipolar, and CMOS transistors and Galium Arsenide (GaAs) transistors, and also in the introduction of new device types and materials. In particular, scaling down device sizes to enhance high frequency performance leads to observable quantum mechanical effects, such as carrier tunneling through potential barriers. These effects led to development of alternative device structures which take advantage of such tunneling phenomenon; such as tunneling, and resonant tunneling, diodes and transistors. For ease of reference, all such structures are hereafter collectively referred to as tunneling diodes (TDs).
Tunneling diodes are generally two terminal devices with conduction carriers tunneling through potential barriers to yield current-voltage curves with portions exhibiting negative differential resistance (NDR). This negative differential resistance characteristic has been used as the basis for a wide range of high performance designs.
Conventionally, tunneling and resonant tunneling diodes have been limited in implementation to GaAs and other high performance processes. Conventional methods have focused on building TDs in GaAs for several reasons; mainly because the speed characteristics and small process features of GaAs processes were conducive to tunneling mechanics. However, performance considerations such as difficulty controlling peak current in TDs, limited their practical application and use. Additionally, since GaAs processes were not practical or cost efficient for high-volume, consumer-related production, TDs were generally limited in application to research and developmental applications.
Previously, the feature size of standard silicon processes, such as CMOS, was not conducive to producing such tunneling structures. Other conventional methods of utilizing tunneling structures in conjunction with standard silicon processes entailed fabrication of a TD structure in a non-silicon process, followed by transferring and bonding (or electrically coupling) the TD structure to a host silicon substrate. While certain performance issues may have thus been addressed, such a process required extra design time and processing steps. The additional design and fabrication costs associated with these approaches is therefore not commercially viable for large volume logic device production.
Thus, conventional implementations of tunneling structures have been used only in discrete form and niche applications, such as high speed pulse and edge generation; produced in costly, high-performance processes. Limitations to conventional tunneling structures include the difficulty in controlling peak current and the lack of an integrated circuit process capable of commercially producing tunneling structures in a commercially viable format.
In the absence of commercially viable TDs, conventional CMOS logic circuit designs have utilized functional components readily available in the CMOS process, such as inverters and logic and transmission gates. Conventional methods have focused on optimizing the design of these components individually, and improving their efficiency when utilized within larger circuits. Such conventional methods inevitably yield device inefficiency; due mainly to layout area, power consumption, and operational speed limits resulting from standard CMOS components.
As performance demands have increased and feature sizes for CMOS processes have decreased, fabrication of tunneling structures in a production CMOS process becomes feasible. Tunnel diode growth on silicon is relatively immature. Recently, CMOS compatible tunnel diodes have been demonstrated to show that a wide range of current densities can be obtained; addressing requirements for imbedded memory and signal processing applications.
Therefore, a system of logic circuitry designs incorporating tunneling structures for a CMOS process is now needed; providing enhanced design performance and efficiency while overcoming the aforementioned limitations of conventional methods.
In the present invention, latch and register circuitry is designed for a CMOS process including quantum mechanical tunneling structures; providing decreased circuit layout area, decreased power consumption, and increased operational speed. NDR and current-voltage (I-V) characteristics of tunneling structures are exploited to provide high-performance, high functionality logic circuitry. Tunneling structures are utilized, replacing numerous conventional CMOS components, to compensate MOS leakage and provide data latching with optimized system performance.
In one embodiment of the present invention, tunneling diodes are paired together in a totem pole fashion, providing a latch functionality. A further embodiment combines the tunneling diode pair with a pass gate and an inverter to provide latch circuitry.
Another embodiment of the present invention combines multiple instances of the latch circuitry taught by the present invention to provide data register circuitry.
A further embodiment of the present invention combines tunneling diode pairs with transistors and inverters; providing flip-flop logic circuitry.